Flip chip technology has been widely used as it allows a high I/O count, high density interconnection scheme with proven performance and reliability. Solder bumps are deposited on contact pads on both chip surfaces and substrate surfaces, and then the chips are flipped and positioned such that the solder bumps are aligned with matching pads of an external circuit. Solder reflow completes the interconnection process, after which underfill material is introduced to fill the spaces about the interconnections.
Solder flip chip assembly can be performed by a solder reflow process. The chip and the substrate should experience the temperature above the melting point of the solder bumps to provide an interconnection between the chip and the substrate. During the reflow process, the coefficient of thermal expansion (CTE) mismatch between, for example, a silicon-based chip and an organic substrate builds thermally induced stress in the flip chip structure. Therefore, when the lower melting temperature solders are used for forming interconnection, the thermally induced stress is decreased. However, while the use of solder having a relatively low melting point can reduce thermally induced stress, it may be subject to failure under high current stress and high temperature storage conditions as it forms intermetallic compounds with under bump metallurgy (UBM) and substrate pad metals at lower temperatures than relatively high melting point solders.